1. Field of the Invention
This invention relates to metal oxide semiconductor field effect transistors (MOSFET). More particularly, this invention relates to devices and methods of dynamically modifying the threshold voltage (V.sub.T) of a MOSFET to maximize the drain-to-source saturation current (I.sub.DS sat) while minimizing the drain-to-source leakage current (I.sub.off).
2. Description of the Related Art
It is well known in the art that the drain-to-source saturation current (I.sub.DSsat) is given by the formula: EQU I.sub.DSsat .beta./2(V.sub.GS -V.sub.T).sup.2 Eq. 1
where: EQU .beta.=W/L KP
W is the width of the channel of the MOSFET. PA1 L is the length of the channel of the MOSFET. PA1 KP is the transconductance parameter of the MOSFET. PA1 V.sub.GS is the gate-to-source voltage, PA1 V.sub.T is the threshold voltage of the MOSFET. PA1 V.sub.TO is the zero bias threshold voltage of the MOSFET. PA1 .gamma. is the body factor or the bulk polarization factor of the MOSFET. PA1 2.sub..phi.F is the surface potential at the source side of the channel of the MOSFET under strong inversion. PA1 V.sub.BS is the bulk-to-source voltage of the MOSFET. PA1 I.sub.DO is the drain-to-source current with the gate-to-source voltage (V.sub.GS) equal to 0. PA1 K is Boltzmans' constant. PA1 T is the temperature. PA1 q is the charge of an electron. PA1 n is determined by the formula: EQU n=C.sub.BC /C.sub.GC +1 PA1 C.sub.BC is the bulk to channel capacitance, which is determined by the bulk-to-source voltage (VBs). PA1 C.sub.GC is the gate-to-channel capacitance.
It is further well known in the art that the threshold voltage V.sub.T is determined by the formula: EQU V.sub.T =V.sub.TO .+-..gamma..sqroot.2.sub..phi.F -V.sub.BS -.sqroot.2.sub..phi.F Eq. 2
where:
FIG. 7 shows a plot 220 of the function of the threshold voltage V.sub.T as a function of the bulk-to-source voltage V.sub.BS. This plot 220 shows the decrease in threshold voltage V.sub.T with an increase in bulk-to-source threshold voltage according to Eq. 2.
The drain-to-source leakage current (I.sub.off) when the gate-to-source voltage of the MOSFET is less than the threshold voltage (V.sub.T) is determined by the formula: ##EQU1## where: W/L is the ratio of the channel width of the MOSFET to the channel length of the MOSFET.
where
As can be seen that by controlling the bulk-to-source voltage (V.sub.BS), the drain-to-source saturation current I.sub.DSsat and the drain-to-source leakage current I.sub.off can be modified.
U.S. Pat. No. 5,614,424 (Wong et al.), assigned to the same assignee as the present invention, and shown in FIG. 1 describes a method for fabricating an accumulated-base junction transistor. Referring to FIG. 1, an n-type dopant material is implanted into a p-type substrate 5 and annealed to form the base region 10 of the accumulated-base BJT. A layer of an insulating material 50 such as silicon dioxide is grown on the p-type substrate 5 and the base region 10 to form the gate oxide area. A layer of polycrystalline silicon 60 is deposited on the gate oxide in the area that forms the gate region that is the base accumulation means. An n.sup.+ -type dopant is then implanted into the base region 10 and annealed to form a base contact region 20. A side wall spacer 65 is deposited adjacent to the polycrystalline silicon gate region 60. A p.sup.+ -type dopant is next implanted and annealed into the base region 10 into areas separated from the base contact region 20 to form a collector region 30 and a emitter region 40. The p.sup.+ -type dopants that are the collector region 30 and the emitter region 40 are self-aligned by the side wall spacer 65 and the polycrystalline silicon gate region 60. The insulating material 50 has openings over the base contact region 20, the collector region 30, the emitter region 40 so as to allow these regions to be connected to external circuitry 70.
Table 1 shows the relative doping levels and the energy levels for the materials that are implanted into the substrate. Table 2 shows the thickness and the temperatures for the deposition of the insulating material that forms the gate oxide and the polycrystalline silicon.
TABLE 1 ______________________________________ Material Doping Electrons/cm.sup.3 Energy ______________________________________ n-well 1e.sup.12 -1e.sup.14 180K ev p.sup.+ 1e.sup.15 -6e.sup.15 30K ev n.sup.+ 1e.sup.15 -6e.sup.15 30k ev ______________________________________
TABLE 2 ______________________________________ Material Thickness Temperature ______________________________________ Thermal Oxide (insulating material) 50.ANG..150.ANG. 800.degree. C.-950.degree. C. Polycrystalline Silicon 1500.ANG.-3000.ANG. 450.degree. C.-650.degree. C. ______________________________________
The base accumulator means (gate) 60 is connected to the emitter 40 and the external circuitry 70. When the external circuitry 70 provides a first voltage to the base accumulator 60 and the emitter region 40, a second voltage to the base contact region 20, and a third voltage to the collector region 30, an electron-type charge (which is the majority carrier) will accumulate at the interface of the insulating material 50 and the base region 10 between the collector region 30 and the emitter region 40. This charge will increase the conductivity of the base region 10, which will increase the transconductance (the ratio of the current flowing into the collector region 30 (I.sub.c) to the voltage developed between the base region 10 and the emitter region 40 (V.sub.be)). FIG. 1b shows a plot X of the current into the base contact region 20 (i.sub.b) and a plot Y of the current into the collector region 30 (I.sub.c) versus the base-emitter voltage (V.sub.be). The change in the base-emitter voltage (V.sub.be) with respect to a 10 fold (decade) change in the current in to the base contact region 20 (I.sub.b) and (I.sub.c) is approximately 60 mv which is similar to that of conventional vertical BJT's.
U.S. Pat. No. 8,326,710 (Joyce et al.) describes a lateral PNP transistor structure is fabricated in a BiCMOS process utilizing the same steps as are used during the. BICMOS process fabricating NPN and CMOS transistors without requiring additional steps. A base N+buried layer formed in the IC substrate that underlies the bipolar PNP transistor. A base Retro and a base contact are formed in the base N+buried layer using the CMOS Retro NWELL mask, etch and N-type introduction sequence. An epitaxial layer of undoped or low doped EPI is deposited across the IC substrate and isolation oxide regions isolating the PNP transistor are grown during the isolation oxide mask, etch and grow sequence. The NPN collector sink definition mask, etch and N-type introduction sequence is used to form a PNP base contact N+sink region to the N-well and N+buried layer. A field oxide spacer FOX is grown during the CMOS active area definition mask, etch and grow sequence for separating the PNP base from the PNP collector. A uniform layer of polysilicon is masked and etched during the POLY definition mask and etch sequence to form a self aligned transistor mask for critically defining the PNP base width and base active region. The PNP collector region and emitter region are introduced through the POLY mask using at least one of the NPN base definition mask, etch, and P-type introduction sequence and PMOS source/drain mask definition, etch, and P-type introduction sequence. The PNP base contact region can be formed using the NPN emitter definition mask sequence. The PNP transistor contact surfaces and metal contacts are thereafter prepared according to conventional procedures.
U.S. Pat. No. 5,360,750 (Yang) provides a method for fabricating a lateral bipolar transistor with a shorter manufacturing cycle time. The method for fabricating NPN lateral bipolar transistors on an N-type substrate begins by implanting a P-type impurity into a predetermined position on the substrate and driving the impurity in to form a P-well in the substrate. An N-type impurity is implanted in predetermined positions in the P-well to form the collector regions of the NPN transistor. The implanting a P-type impurity into predetermined positions in the P-well to form contacts for the base electrodes of the NPN transistor. An N-type impurity is then implanted into predetermined positions in the P-well and the collector region, to form respective emitter electrodes and collector electrodes of the NPN transistor. A field oxide layer is formed over the NPN transistors and metal contacts are formed to the base electrode, the collector electrode and the emitter electrode of the NPN transistor.
U.S. Pat. No. 5,268,650 (Schnabel) describes a circuit for an operational amplifier which provides very high amplification of an input signal with low currents while, at the same time; not increasing the offset voltage drift. The amplifier has an input stage, at lest one intermediate stage, and an output stage each formed of MOSFET's and bipolar transistors.